1. Field of the Invention
The invention relates to methods for designing integrated circuits, and particularly to a system for determining the physical placement and interconnection of components forming an integrated circuit.
2. Description of Related Art
An IC design engineer typically models a circuit using a hardware description language (HDL) to describe the behavior of the various components making up a circuit and the manner in which those components are interconnected. The design engineer then programs a circuit simulator to simulate circuit behavior based on the HDL circuit model. Since the HDL model is a relatively high level behavioral model of the circuit, the initial circuit simulation does not take into account the timing and other constraints of the semiconductor technology that will implement the IC,
After verifying circuit logic, the design engineer usually employs computer-aided design and engineering tools to convert the high-level HDL circuit model into a lower-level, technology specific, circuit model, such as a netlist. In this model the circuit components are defined in terms of models of physical circuit cells (logic gates, transistors, etc.) that will eventually implement the components in the IC. The design engineer may then use a simulator to again simulate circuit operation based on the netlist model to verify circuit logic. Since the netlist model is more closely related to the eventual physical realization of the IC, the simulator or special timing verification tools can verify circuit timing. However timing verification at this stage of the design is still not entirely accurate since the netlist model does not take into account the actual physical layout on an IC chip of the cells that will form the circuit. Having verified the logic and at least partially verified timing of the netlist circuit model, the design engineer is ready to begin designing the physical layout and interconnection of circuit cells on the IC with the aid of computer-aided placement and routing tools.
Placement and routing is typically an iterative process. After establishing a trial placement of cells in the substrate area, the system generates a trial routing for the placement. A trial routing does not determine actual signal path routes between cells but makes an estimate as to whether there is sufficient space available in the substrate area to route the signal paths and estimates the length and impedance characteristics of those paths that affect the time required for signals to travel over the paths. If a suitable trial routing path cannot be established for the trial placement, the trial placement may be modified, and a new trial routing is attempted. The process can be repeated iteratively until suitable placement and trial routing is obtained. At this point the physical design is typically converted back into an HDL model that takes into account not only the nature of the semiconductor technology implementing the IC but also the signal timing influences of the placement and trial routing. Simulation and timing verification tools are then employed to verify circuit logic and timing. Thereafter the design engineer uses routing tools to develop a detailed routing for the IC defining the specific paths interconnecting the circuit cells. The placement and detailed routing can then be converted into HDL format and again subjected logic and timing verification. Thereafter the detailed placement and routing specification provide a basis for defining masks for fabricating the IC.
Divide-and-Conquer Placement Systems
Some placement algorithms employ a xe2x80x9cdivide-and-conquerxe2x80x9d approach to circuit placement which successively subdivides the substrate area of an IC into smaller and smaller areas. Whenever an area is subdivided into two (or more) smaller areas, the algorithm looks for a way to allocate cells of the original area among the smaller areas in a way that minimizes the number of signal paths crossing partition lines. This tends to cluster interconnected cells together, thereby reducing the time signals need to travel between cells. Since there are usually a huge number of possible cell allocations that can be made after each successive partitioning, such placement systems normally use various search techniques to try to find a most suitable placement allocation. For example a system may initially randomly allocate cells and then move individual cells from partition to partition in hopes of finding a better placement.
Design Partitioning
The HDL and netlist models are typically hierarchical in nature in that the circuit is defined by several interconnected modules, each of which in turn may be defined by several by lower level modules. Each module typically has some identifiable logical function. For example a design for a microprocessor may include top level modules such as an instruction processor module, a cache controller module, and a clock controller module. The instruction processor module may be formed, for example, by an instruction decoder module, an arithmetic logic unit module, etc. The instruction decoder module may in turn be formed by a number of logic gate modules, each of which is defined at the lowest level of the design hierarchy by a set low-level cells such as transistors or logic gates.
One undesirable effect of a divide-and-conquer placement algorithm is that it discards the hierarchical nature of the design and does not place the cells of any module in a well-defined area of an IC. Cells of closely interconnected modules are usually intermingled to minimize signal path lengths. This makes it impossible for the designer to substantially modify a logic module within an IC design without repeating the placement and routing process for the entire IC. Design engineers therefore often like to xe2x80x9cpartitionxe2x80x9d an IC design along modular lines and place each partition in an identifiable area of the IC substrate. A designer will also place various xe2x80x9cstandardxe2x80x9d cells in separately identifiable boxes (xe2x80x9chard fence areasxe2x80x9d) that are not altered during the placement and routing process. IC designers also like to partition a large IC design along modular lines so each partition can be separately placed and routed by several concurrently operating placement and routing systems. This speeds up the placement and routing process.
In order to partition a design, the design engineer initially develops a xe2x80x9cfloor planxe2x80x9d of the IC indicating the size, shape and relative position of each partition, along with a xe2x80x9cpin assignmentxe2x80x9d plan defining points (pins) wherein signals cross partition boundaries. The floor plan may also define any hard fence areas included within each partition. The design engineer then develops a separate specification for each partition so that placement and routing can proceed independently for each partition consistent with the floor and pin assignment plans.
When developing a floor plan for partitioning an IC, the design engineer can usually roughly estimate the size of each partition based on information contained in the netlist including the number and sizes of transistors and other components that form the modules to be included in the partition. However since the design engineer often does not have as much information on which to base the choice of partition shape, position and pin assignments, the initial shape, position and pin assignments for each partition are often based on little more than xe2x80x9ceducated guessesxe2x80x9d.
Since floor and pin assignment plans developed in such manner often do not directly lead to placement and routing plans satisfying circuit criteria, a design engineer may have to iteratively modify the floor and pin assignment plans several times before arriving at plans that permit satisfactory placement and routing. This labor intensive iterative process can be slow to converge to an acceptable IC layout, and the final layout my be less than optimal in many respects.
What is needed is an IC placement and routing system that automatically produces initial floor and pin assignment plans that can lead to optimal placement and routing of circuit components.
The present invention relates to a system for placing and routing an integrated circuit (IC) designed as a hierarchy of circuit modules. The invention is used when the circuit design is to be partitioned along modular lines, with each partition being placed in a separate, identifiable area of an IC substrate.
In accordance with one aspect of the invention, the system performs an initial xe2x80x9cfull-chipxe2x80x9d divide-and-conquer trial placement and routing of the entire IC design in a manner that does not take into account the manner in which the circuit is to be partitioned but which is biased toward clustering of cells of each given module together. The system then creates a floor plan for the IC that establishes the size and shape and an initial positioning of areas of IC substrate that are to contain the modules forming each partition. The size, shape and position of each partition defined by floor plan is based on the actual size, shape and relative positions of areas of the trial placement that contain those modules.
In accordance with another aspect of the invention, the system also creates a pin assignment plan for each partition based on the trial placement and routing plans.
In accordance with a further aspect of the invention, the system treats each of the partitions as a separate IC design and separately optimizes cell placement and routing within each partition. The system also optimizes xe2x80x9ctop levelxe2x80x9d positioning of the partitions themselves within the IC substrate and routing therebetween without changing the size or shape of the partitions or their pin assignments.
Since the size, shape, pin assignments and initial positioning of each partition are based on a whole-chip trial placement and routing, the system typically produces floor and pin assignment plans that quickly converge to an acceptable placement and routing plan that makes efficient use of IC substrate space.
It is accordingly an object of the invention to provide a placement and routing system that automatically produces initial floor and pin assignment plans that determines the appropriate size, shape, positions of circuit partitions with high accuracy so that a detailed placement and routing process can thereafter quickly optimize placement and routing of components forming the partitions.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.